1. Field of the Invention
The present invention relates to a semiconductor device and more particularly to an internal voltage generator for allowing stable voltage supply to an internal circuit.
2. Description of Related Art
With reference to the accompanying drawings, an internal voltage generator according to a conventional art will now be described.
FIG. 1 is a block diagram for showing a general idea of the conventional internal voltage generator.
As shown in FIG. 1, a semiconductor device includes internal circuit 11 and internal voltage generation section 12 for applying a voltage to the internal circuit 11.
The internal voltage generation section 12 converts an external supply voltage (Vcc) into an internal supply voltage (Vint) before supplying the voltage to the internal circuit 11.
Such internal voltage generator as shown in FIG. 1 is a down-converted voltage generator that does not immediately apply the external supply voltage (Vcc) to the internal circuit 11 but converts the external supply voltage (Vcc) into the internal voltage (Vint) before supply to the internal circuit 11. Therefore, the internal voltage (Vint) that is equal to or lower than the external supply voltage (Vcc) is supplied to the internal circuit 11 in this down-converted voltage generator.
As illustrated, the voltage is stably supplied to the internal circuit, so the internal circuit 11 becomes insensitive to the external supply voltage, thus stably operating.
There are also advantages of protecting the internal circuit 11 from over-supplied external voltage and reducing power consumption.
FIG. 2 illustrates a first embodiment of the internal voltage generator according to the conventional art.
The device shown in FIG. 2 is an analog voltage generator, which comprises comparator 21, reference voltage generator 22, first drive transistor 23, and internal circuit 24.
The comparator 21 compares an internal voltage (Vint) applied to the internal circuit 24 with a reference voltage (Vref) output from the reference voltage generator 22.
The comparator 21 is constituted by a differential amplifier. The comparator 21 has an inverting terminal coupled to the reference voltage generator 22 and a non-inverting terminal coupled to an internal voltage input terminal of the internal circuit 24.
An output voltage (SCas) of the comparator 21 is applied to a gate as a control signal over the first drive transistor 23.
Such conventional analog voltage generator will be described with reference to a voltage waveform diagram shown in FIG. 3.
FIG. 3 shows voltage waveforms appearing in the internal voltage generator depicted in FIG. 2. It is assumed that the reference voltage (Vref) generated from the reference voltage generator 22 has the same level as an ideal internal voltage (Vint).
Primarily, the internal voltage (Vint) is consumed for the operation of the internal circuit 24. If the internal voltage is lower than the reference voltage (Vref), the output voltage (SCas) of the comparator 21 becomes lower. The lowered output voltage of the comparator 21 increases a value of a Vsg (a voltage flowing between a gate and a source) in the first drive transistor 23, thereby increasing driving power.
Charge thus inward flows from the external supply voltage, so the lowered internal voltage (Vint) increases.
On the other hand, if the internal supply voltage (Vint) is higher than the reference voltage (Vref), the output voltage (SCas) of the comparator 21 becomes higher, so the inflow of the charge from the external supply voltage is limited. Therefore, there is no further increase of the internal supply voltage.
Essentially, the internal supply voltage (Vint) has a feature of controlling the driving power of the first drive transistor 23 with an analog level so as to maintain the same level as the reference voltage (Vref).
FIG. 4 shows a configuration of an internal voltage generator according to a second embodiment of the conventional art.
Compared with the one depicted in FIG. 2, the internal voltage generator depicted in FIG. 4 further comprises buffer 25 for buffering the output of the comparator 21 and second drive transistor 26. An output terminal in the buffer 25 is connected to a gate of the second drive transistor 26.
The buffer 25 is composed of first inverter 25a and second inverter 2b connected in serial.
Such internal voltage generator according to the second embodiment of the conventional art uses analog mode together with digital mode.
This structural feature will be described with reference to FIG. 5 showing voltage waveforms.
As shown in FIG. 5, if the internal supply voltage (Vint) applied to the internal circuit 24 is lower than the reference voltage (Vref), the output voltage (SCas) of the comparator 21 becomes lower.
The lowered output voltage of the comparator 21 increases the value of the Vsg of the first drive transistor 23, thus increasing the driving power.
Consequently, the external supply voltage (Vcc) flows into the internal supply voltage.
The lowered output of the comparator 21 becomes lower than a threshold voltage of the first inverter 25a, so an output of the second inverter 25b becomes logic "0" finally.
Namely, a level of the output of the second inverter 25b becomes equal to a level of a grounding voltage (Vss), and a level of the Vsg of the second drive transistor 26 becomes equal to a level of the external supply voltage (Vcc).
Hence, the charge flows into the internal supply voltage (Vint) via the second drive transistor 26, thereby increasing the internal supply voltage (Vint).
If it is assumed that sizes of the first and second transistors 23 and 26 are equal to each other, the Vsg value of the second drive transistor 26 exceeds the Vsg value of the first drive transistor 23. The inflow of charge via the second drive transistor 26 is larger than the inflow of charge via the first drive transistor 23.
On the other hand, if the internal supply voltage (Vint) exceeds the reference voltage (Vref), the output voltage of the comparator 21 increases, decreasing the driving power of the first drive transistor 23.
The inflow of charge from the external supply voltage (Vcc) is thus limited.
In addition, the output of the comparator 21 becomes higher than the threshold voltage of the first inverter 25a, so the output of the second inverter 25b becomes logic "1"
Consequently, the second drive transistor 26 becomes turned OFF, thus cutting off the charge flowing from the external supply voltage (Vcc) into the internal supply voltage (Vint).
Therefore, increase of the internal supply voltage (Vint) flowing into the internal circuit 24 is suppressed.
However, such conventional internal voltage generator has the following defects.
Primarily, in the first embodiment, it happens that the driving ability of the first drive transistor is limited. To enhance the driving ability of the first drive transistor, the size of the transistor should be larger, but this results in increase of the load of a voltage applied to the gate in the first drive transistor. Consequently, reply speed of a differential amplifier becomes lower. This causes a problem that a level of the internal supply voltage considerably drops when much internal supply voltage (Vint) is required for a short time.
In the second embodiment, the analog-digital internal voltage generator swings a voltage applied to the gate in the second drive transistor up to a full CMOS level, thus enhancing the driving ability of the second drive transistor.
However, it is highly possible that there occurs severe overshoot of the internal supply voltage (Vint). In other words, a buffer (a first inverter and a second inverter) for converting an analog level into a digital level is required for the voltage applied to the gate in the second drive transistor. The addition of the buffer causes time delay.
When the internal supply voltage (Vint) is lower than the reference voltage (Vref), so the voltage applied to the gate in the second drive transistor is equal to the grounding voltage, the second drive transistor is turned ON and supplies charge to the internal supply voltage. Since the second drive transistor is turned OFF via the comparator and buffer, the time delay is caused. The overshoot thus occurs in the internal supply voltage (Vint).